Skip to content
The Neutral Atom SDK
Address impl
Initializing search
bloqade
Home
Bloqade Digital
Digital Tutorials
Bloqade Analog
Analog Tutorials
qBook
API Reference
Blog
QuEra Computing
The Neutral Atom SDK
bloqade
Home
Home
Installation
Background
Manifesto
Quick Start
Quick Start
Bloqade Digital
Bloqade Digital
Bloqade Analog
Bloqade Analog
Contributing
Bloqade Digital
Bloqade Digital
Domain specific languages
Domain specific languages
QASM2
SQUIN
Stim
Compilation process
Simulation
Simulation
Simulation devices
Tasks
Interoperability with Cirq
Interoperability with Cirq
Converting cirq to squin
Converting squin to Cirq
Digital Tutorials
Digital Tutorials
QASM2 examples
QASM2 examples
Quantum Fourier Transform
GHZ State Preparation with Parallelism
Pauli Exponentiation for Quantum Simulation
Repeat Until Success with STAR Gadget
QAOA
Squin dialect examples
Squin dialect examples
Deutsch-Jozsa Algorithm
GHZ State Preparation with Squin
Integration with other SDKs
Integration with other SDKs
GHZ State preparation and noise
Bloqade Analog
Bloqade Analog
Migration Guide to Bloqade Analog
Quickstart
Background
Gotchas
Contributing
Contributing
Ask a Question
Design Philosophy and Architecture
Community Slack
Design Philosophy and Architecture
Reporting a Documentation Issue
Requesting new Features
Providing Feedback
Reporting a Bug
Builder
Builder
Builder Overview
Build Workflow
Hardware Reference
Analog Tutorials
qBook
API Reference
API Reference
Bloqade Digital
Bloqade Digital
Device
Task
Types
Analysis
Analysis
Address
Address
Analysis
Impls
Lattice
Fidelity
Fidelity
Analysis
Measure id
Measure id
Analysis
Impls
Lattice
Cirq utils
Cirq utils
Lineprog
Parallelize
Noise
Noise
Conflict graph
Model
Transform
Pyqrack
Pyqrack
Base
Device
Reg
Target
Task
Noise
Noise
Native
Qasm2
Qasm2
Core
Glob
Parallel
Uop
Squin
Squin
Op
Qubit
Runtime
Wire
Noise
Noise
Native
Qasm2
Qasm2
Glob
Groups
Noise
Parallel
Types
Dialects
Dialects
Glob
Indexing
Inline
Parallel
Core
Core
Address
Stmts
Expr
Expr
Stmts
Noise
Noise
Fidelity
Model
Stmts
Uop
Uop
Schedule
Stmts
Emit
Emit
Base
Gate
Main
Target
Impls
Impls
Noise
Parse
Parse
Ast
Build
Lowering
Parser
Print
Visitor
Passes
Passes
Fold
Glob
Lift qubits
Noise
Parallel
Py2qasm
Qasm2py
Unroll if
Rewrite
Rewrite
Desugar
Glob
Insert qubits
Native gates
Parallel to glob
Parallel to uop
Register
Uop to parallel
Noise
Noise
Heuristic noise
Remove noise
Qbraid
Qbraid
Lowering
Schema
Simulation result
Target
Rewrite
Rewrite
Passes
Passes
Canonicalize ilist
Rules
Rules
Flatten ilist
Inline getitem ilist
Split ifs
Squin
Squin
Groups
Lowering
Parallel
Qubit
Types
Wire
Analysis
Analysis
Address impl
Address impl
Table of contents
address_impl
Schedule
Nsites
Nsites
Analysis
Impls
Lattice
Cirq
Cirq
Lowering
Noise
Noise
Rewrite
Stmts
Op
Op
Number
Rewrite
Stdlib
Stmts
Traits
Types
Rewrite
Rewrite
U3 to clifford
Canonicalize
Desugar
Remove dangling qubits
Wrap analysis
Stdlib
Stdlib
Channel
Gate
Stim
Stim
Groups
Dialects
Dialects
Auxiliary
Auxiliary
Emit
Interp
Lowering
Types
Stmts
Stmts
Annotate
Const
Collapse
Collapse
Emit str
Stmts
Stmts
Measure
Pp measure
Reset
Gate
Gate
Emit
Stmts
Stmts
Base
Clifford 1q
Clifford 2q
Control 2q
Pp
Noise
Noise
Emit
Stmts
Emit
Emit
Stim str
Parse
Parse
Lowering
Passes
Passes
Simplify ifs
Squin to stim
Rewrite
Rewrite
Ifs to stim
Py constant to stim
Qubit to stim
Squin measure
Squin noise
Util
Wire identity elimination
Wire to stim
Upstream
Upstream
From squin
Visual
Visual
Animation
Animation
Animate
Base
Gate event
Runtime
Runtime
Aod
Atoms
Ppoly
Qpustate
Utils
Bloqade Analog
Bloqade Analog
Atom arrangement
Constants
Factory
Migrate
Serialize
Builder
Builder
Args
Assign
Coupling
Drive
Field
Parallelize
Pragmas
Route
Sequence builder
Spatial
Start
Typing
Waveform
Backend
Backend
Bloqade
Braket
Quera
Parse
Parse
Builder
Stream
Trait
Compiler
Compiler
Analysis
Analysis
Common
Common
Assignment scan
Check slices
Is constant
Is hyperfine
Scan channels
Scan variables
Hardware
Hardware
Channels
Lattice
Piecewise constant
Piecewise linear
Python
Python
Waveform
Passes
Passes
Emulator
Hardware
Hardware
Components
Define
Units
Rewrite
Rewrite
Common
Common
Add padding
Assign to literal
Assign variables
Canonicalize
Flatten
Python
Python
Waveform
Emulate
Emulate
Sparse operator
Ir
Ir
Atom type
Emulator
Space
State vector
Ir
Ir
Analog circuit
Scalar
Control
Control
Field
Pulse
Sequence
Waveform
Traits
Traits
Append
Canonicalize
Hash
Slice
Location
Location
Bravais
Location
Routine
Routine
Base
Bloqade
Braket
Params
Quera
Submission
Submission
Base
Braket
Load config
Mock
Quera
Ir
Ir
Braket
Capabilities
Parallel
Task results
Task specification
Task
Task
Base
Batch
Bloqade
Braket
Braket simulator
Exclusive
Quera
Blog
Blog
Archive
Archive
2025
2023
QuEra Computing
Table of contents
address_impl
Address impl
Back to top